SIS : A System for Sequential Circuit Synthesis

TLDR

SIS is an interactive, modular tool built on MISII that supports synthesis and optimization of sequential circuits, integrating multiple algorithms and serving as a framework for testing and automatic design. The paper offers an overview of the SIS system. SIS transforms state transition tables, STGs, or logic‑level descriptions into optimized net‑lists while preserving behavior, using STG and ASTG manipulation, logic optimization, verification algorithms, and PGA synthesis, as illustrated by a tutorial example.

Abstract

SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII [5] and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits. This paper provides an overview of SIS. The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS.