Delay Fault Testing

Delay Fault Testing is a test methodology within the broader class of structural fault testing techniques that specifically targets defects causing unacceptable propagation delays in digital circuits by verifying whether signal transitions occur within prescribed time constraints.

485

Publications

17.9K

Citations

769

Authors

212

Institutions

Publications per year

2017–2026

10

Authors

769

  1. SR
    S.M. Reddy

    University of Iowa, United States

    40 publications · 2.3K citations

    24

    h-index

  2. KC
    Kwang‐Ting Cheng

    University of California, Santa Barbara, United States

    30 publications · 1.5K citations

    20

    h-index

  3. IP
    Irith Pomeranz

    University of Iowa, United States

    31 publications · 1.2K citations

    18

    h-index

  4. VD
    Vishwani D. Agrawal

    AT&T (United States), United States

    26 publications · 759 citations

    17

    h-index

  5. SP
    S. Pravossoudovitch

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    17 publications · 388 citations

    14

    h-index

1–5 of 769

Venues

  1. 28

    h-index

  2. 14

    h-index

  3. IEEE Transactions on Computers

    13 publications · 623 citations

    12

    h-index

  4. IEEE Design & Test of Computers

    10 publications · 1.1K citations

    10

    h-index

  5. Journal of Electronic Testing

    JETTA · 10 publications · 188 citations

    10

    h-index

1–5