Xijiang Lin

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Santiago Remersaro, Xijiang Lin, Zhuo Zhang et al. · Proceedings/Proceedings - International Test Conference · 2006 · 236 citations

Engineering, Electronic Design Automation, Computer Architecture +23

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

Xijiang Lin, Kun-Han Tsai, Chen Wang et al. · Proceedings - Asian Test Symposium/Proceedings · 2006 · 132 citations

Engineering, New Atpg Methodology, Mem Testing +16

On static test compaction and test pattern ordering for scan designs

Xijiang Lin, Janusz Rajski, Irith Pomeranz et al. · 2002 · 69 citations

Engineering, Computational Complexity, Fault Coverage Curve +21

Low Power Scan Shift and Capture in the EDT Environment

Dariusz Czysz, Mark Kassab, Xijiang Lin et al. · 2008 · 57 citations

Engineering, Test Compression Environment, Computer Architecture +20

Low-Power Scan Operation in Test Compression Environment

Dariusz Czysz, Mark Kassab, Xijiang Lin et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009 · 56 citations

Hardware Security, Power-aware Design, Electrical Engineering +15