Janusz Rajski - Concepedia

Author

Janusz Rajski

Mentor Technologies ORCID

Also Known As

Anne Gattiker, J-Y Choi, J. Rajski, Janusz Rajski, Rajski, Janusz

250

Publications

6.6K

Citations

H-Index

133

Concepts

All Affiliations

Mentor Technologies Poznań University of Technology Siemens (Hungary)McGill University University of Iowa

About

Janusz Rajski is an author at Mentor Technologies specializing in engineering, computer engineering, and design for testing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	42	125	5.9K
2	Education	10	10	561
3	Medicine	2	2	99
4	Health Sciences	1	1	34
5	Management	1	1	88

Janusz Rajski

134

Publications

6.1K

Citations

H-Index

Page 1

	Year	Citations
Embedded Deterministic Test Janusz Rajski, Jerzy Tyszer, Mark Kassab, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringMem TestingVerificationComputer ArchitectureTest Data Generation	2004	518
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, IEEE Transactions on Computers EngineeringMem TestingVerificationComputer ArchitectureEntire Test Set	1995	405
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Proceedings/Proceedings - International Test Conference EngineeringElectronic Design AutomationComputer ArchitectureComputer-aided DesignHardware Security	2006	236
A method of fault analysis for test generation and fault diagnosis Henry Cox, Janusz Rajski IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Fault DiagnosisEngineeringVerificationDiagnosisTest Data Generation	1988	158
High-frequency, at-speed scan testing Xijiiang Lin, Ron Press, Janusz Rajski, IEEE Design & Test of Computers Internal PllEngineeringMeasurementMem TestingComputer Architecture	2003	155
Testing and diagnosis of interconnects using boundary scan architecture A.S.M. Hassan, Janusz Rajski, V.K. Agarwal EngineeringMem TestingDiagnosisBoundary Scan ArchitectureInterconnect (Integrated Circuits)	2003	140
Convolutional compaction of test responses Janusz Rajski, Jerzy Tyszer, Chen Wang, EngineeringCompaction RatiosConvolutional CompactorMem TestingComputer Architecture	2004	139
An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers S. Venkataraman, Janusz Rajski, Sybille Hellebrand, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) EngineeringVlsi DesignPseudo-random SequenceAnalog DesignComputer Architecture	2005	102
Test data decompression for multiple scan designs with boundary scan Janusz Rajski, Jerzy Tyszer, N. Zacharia IEEE Transactions on Computers Numerical AnalysisDecompression DeviceEngineeringMem TestingComputer Architecture	1998	93
Test responses compaction in accumulators with rotate carry adders Janusz Rajski, Jerzy Tyszer IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringMeasurementMem TestingExperimental TechnologyComputer Architecture	1993	88

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