Jeff Rearick

Too much delay fault coverage is a bad thing

Jeff Rearick · 2002 · 264 citations

Engineering, Safety Science, Computer Architecture +18

Fast and accurate CMOS bridging fault simulation

Jeff Rearick, J.H. Patel · 2002 · 83 citations

Hardware Security, Hybrid Technique, Electrical Engineering +14

Calibrating clock stretch during AC scan testing

Jeff Rearick, Richard W. Rodgers · 2006 · 64 citations

Engineering, Measurement, Education +18

IJTAG (Internal JTAG): A Step Toward a DFT Standard

Jeff Rearick, Bill Eklow, K. Posse et al. · 2006 · 52 citations

Hardware Security, Engineering, Inspection +15

Cell-aware analysis for small-delay effects and production test results from different fault models

Friedrich Hapke, Juergen Schloeffel, W. Redemund et al. · 2011 · 42 citations

Engineering, Vlsi Design, Additional Defect Detections +20