Transition Fault Simulation

TLDR

Delay fault testing is increasingly critical for complex VLSI chips, especially for gate‑array fragments that require a general delay‑fault model and practical test‑pattern generation. The authors propose a transition‑fault model that, combined with parallel‑pattern, single‑fault propagation, offers an efficient delay‑fault simulation approach. The model employs parallel‑pattern, single‑fault propagation to efficiently simulate delay faults. Experiments on ten benchmark designs show that transition‑fault simulation adds less than 10% overhead compared to stuck‑fault simulation, and the authors integrated add‑ons into a stuck‑fault simulator to support it.

Abstract

Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designs and discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.