Design For Scanability

Design for Scanability is a design methodology within the field of digital circuit testing that integrates specialized sequential structures into a circuit’s architecture to enable controlled and observable state transitions during test application, thereby facilitating efficient fault detection and diagnosis.

282

Publications

11.6K

Citations

616

Authors

193

Institutions

Publications per year

2017–2026

8

Authors

616

  1. XW
    Xiaoqing Wen

    Kyushu Institute of Technology, Japan

    13 publications · 500 citations

    13

    h-index

  2. SR
    S.M. Reddy

    University of Iowa, United States

    15 publications · 1.1K citations

    13

    h-index

  3. JR
    Janusz Rajski

    Mentor Technologies, United States

    14 publications · 1.4K citations

    13

    h-index

  4. SK
    Seiji Kajihara

    Kyushu Institute of Technology, Japan

    12 publications · 437 citations

    12

    h-index

  5. IP
    Irith Pomeranz

    University of Iowa, United States

    14 publications · 848 citations

    12

    h-index

1–5 of 616

Venues

  1. 11

    h-index

  2. IEEE Design & Test of Computers

    10 publications · 484 citations

    10

    h-index

  3. 9

    h-index

  4. Journal of Electronic Testing

    JETTA · 9 publications · 201 citations

    9

    h-index

  5. IEEE Transactions on Computers

    8 publications · 696 citations

    8

    h-index

1–5