Design For Scanability
Design for Scanability is a design methodology within the field of digital circuit testing that integrates specialized sequential structures into a circuit’s architecture to enable controlled and observable state transitions during test application, thereby facilitating efficient fault detection and diagnosis.
282
Publications
11.6K
Citations
616
Authors
193
Institutions
Publications per year
2017–2026
8
Parents
282
LFSR-coded test patterns for scan designs
B. Koenemann · Medical Entomology and Zoology · 1991 · 510 citations
Reducing test application time for full scan embedded cores
İlker Hamzaoğlu, J.H. Patel · 2003 · 337 citations
V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations
1–5 of 282
616
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193
Mentor Technologies
Tulsa, United States
15 h-index
41 publications
2.4K citations
University of Iowa
Iowa City, United States
14 h-index
30 publications
2.2K citations
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Montpellier, France
14 h-index
38 publications
2.4K citations
Kyushu Institute of Technology
Kitakyushu, Japan
13 h-index
52 publications
1.8K citations
Purdue University West Lafayette
West Lafayette, United States
11 h-index
14 publications
537 citations
Intel (United States)
Santa Clara, United States
10 h-index
18 publications
825 citations
Siemens (Hungary)
Budapest, Hungary
10 h-index
27 publications
2.4K citations

Poznań University of Technology
Poznan, Poland
10 h-index
15 publications
601 citations
1–8 of 193
11 publications · 910 citations
11
h-index
10 publications · 484 citations
10
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9 publications · 255 citations
9
h-index
JETTA · 9 publications · 201 citations
9
h-index
8 publications · 696 citations
8
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