Seiji Kajihara

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

Seiji Kajihara, Irith Pomeranz, K. Kinoshita et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1995 · 222 citations

Engineering, Verification, Test Data Generation +21

On low-capture-power test generation for scan testing

Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara et al. · 2005 · 165 citations

Hardware Security, Power-aware Design, Electrical Engineering +14

Low-capture-power test generation for scan-based at-speed testing

Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima et al. · 2006 · 125 citations

Hardware Security, Electrical Engineering, Engineering +14

Invisible delay quality - SDQM model lights up what could not be seen

Yasuo Satô, Shuji Hamada, Toshiyuki Maeda et al. · 2006 · 119 citations

Invisible Delay Quality, Reliability Engineering, Engineering +13

XID: Don't Care Identification of Test Patterns for Combinational Circuits

Kohei Miyase, Seiji Kajihara · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004 · 102 citations

Engineering, Verification, Test Data Generation +17