Seiji Kajihara - Concepedia

Author

Seiji Kajihara

Also Known As

Jerzy Tyszer, Li Jiang, S Kajihara, S. KAJIHARA, S. Kajihara, Seiji KAJIHARA, Seiji Kajihara, Seiya Kajihara, Shuta Kajihara, Tomokazu Yoneda

285

Publications

3.2K

Citations

H-Index

Concepts

All Affiliations

Kyushu Institute of Technology University of Iowa Syntek Technologies (United States)University of Wisconsin–Madison The University of Osaka

About

Seiji Kajihara is an author at Kyushu Institute of Technology specializing in engineering, computer engineering, and software testing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	30	62	2.7K
2	Education	7	7	349
3	Health Sciences	4	4	187
4	Medicine	2	2	37
5	Public Health	1	1	17

Seiji Kajihara

Publications

2.8K

Citations

H-Index

Page 1

	Year	Citations
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits Seiji Kajihara, Irith Pomeranz, K. Kinoshita, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVerificationTest Data GenerationFormal VerificationNew Test Vector	1995	222
On low-capture-power test generation for scan testing Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Hardware SecurityPower-aware DesignElectrical EngineeringScan TestingEngineering	2005	165
Low-capture-power test generation for scan-based at-speed testing Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Hardware SecurityElectrical EngineeringEngineeringVlsi DesignLow-capture-power Test Generation	2006	125
Invisible delay quality - SDQM model lights up what could not be seen Yasuo Satô, Shuji Hamada, Toshiyuki Maeda, Invisible Delay QualityReliability EngineeringEngineeringHardware ReliabilitySdqm Model	2006	119
XID: Don't Care Identification of Test Patterns for Combinational Circuits Kohei Miyase, Seiji Kajihara IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVerificationTest Data GenerationSoftware AnalysisFormal Verification	2004	102
On test data volume reduction for multiple scan chain designs S.M. Reddy, Kohei Miyase, Seiji Kajihara, EngineeringComputer ArchitectureTest Data VolumeComputational TestingModeling And Simulation	2003	95
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, EngineeringMem TestingComputer ArchitectureExcessive Jr DropHardware Security	2006	91
Test vector modification for power reduction during scan testing Seiji Kajihara, Kunio Ishida, Kohei Miyase EngineeringMeasurementTest Vector ModificationPower Optimization (Eda)Education	2003	85
Selection of potentially testable path delay faults for test generation Akira Murakami, Seiji Kajihara, Tetsuo Sasao, EngineeringHardware Verification LanguageVerificationComputer ArchitectureTest Data Generation	2002	83
Compact test sets for high defect coverage S.M. Reddy, Irith Pomeranz, Seiji Kajihara IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Reliability EngineeringEngineeringSoftware TestingTest CoverageTest Generation Procedures	1997	80

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