Kohei Miyase

XID: Don't Care Identification of Test Patterns for Combinational Circuits

Kohei Miyase, Seiji Kajihara · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004 · 102 citations

Engineering, Verification, Test Data Generation +17

On test data volume reduction for multiple scan chain designs

S.M. Reddy, Kohei Miyase, Seiji Kajihara et al. · 2003 · 95 citations

Engineering, Computer Architecture, Test Data Volume +16

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase et al. · 2006 · 91 citations

Engineering, Mem Testing, Computer Architecture +17

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments

Aibin Yan, Xiangfeng Feng, Yuanjie Hu et al. · IEEE Transactions on Aerospace and Electronic Systems · 2019 · 90 citations

Engineering, Vlsi Design, Computer Architecture +16

Test vector modification for power reduction during scan testing

Seiji Kajihara, Kunio Ishida, Kohei Miyase · 2003 · 85 citations

Engineering, Measurement, Test Vector Modification +17