2005 · 165 citations · 24 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingLow-power DesignTest DevelopmentDesign For TestabilityDynamic Power ReductionLow-power Digital Circuit DesignPower AnalysisPower ManagementPower OptimizationFault CoverageLow-power Design For TestabilityScan DesignSwitching Activity AnalysisSwitching Activity ReductionTest GenerationYield Loss PreventionYield Loss Reduction
Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0's and 1's to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
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A distributed BIST control scheme for complex VLSI devices
Y. Zorian · 2002 · 543 citations
Engineering, Computer Engineering, Electrical Engineering +12
V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations