Concepedia

On-chip Test Pattern Generation

On-Chip Test Pattern Generation is a design for testability technique that refers to the autonomous synthesis of test stimuli within an integrated circuit, distinguished by its localized, hardware-based execution to reduce external test data volume and enhance fault coverage.

166

Publications

5.7K

Citations

430

Authors

139

Institutions

Publications per year

2017–2026

17

Parents

Publications

166

Embedded Deterministic Test

Janusz Rajski, Jerzy Tyszer, Mark Kassab et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004 · 526 citations

, , +13

A SmartBIST variant with guaranteed encoding

B. Koenemann, C. Barnhart, Brion Keller et al. · 2002 · 269 citations

, , +15

Testing the interconnect of RAM-based FPGAs

M. Renovell, J.M. Portal, Joan Figueras et al. · IEEE Design & Test of Computers · 1998 · 159 citations

, , +15

A BIST scheme for on-chip ADC and DAC testing

Jiun-Lang Huang, Chee-Kian Ong, Kwang‐Ting Cheng · 2000 · 149 citations

, , +17

Test Pattern Generation for Realistic Bridge Faults in CMOS ICs

F.J. Ferguson, T. Larrabee · 2005 · 138 citations

, , +16

1–5 of 166

Authors

430

  1. KC
    Krishnendu Chakrabarty

    Duke University, United States

    6 publications · 132 citations

    6

    h-index

  2. HW
    Hans-Joachim Wunderlich

    University of Stuttgart, Germany

    6 publications · 151 citations

    6

    h-index

  3. PC
    P.P. Chaudhuri

    Indian Institute of Technology Kharagpur, India

    5 publications · 98 citations

    5

    h-index

  4. KL
    Kuen-Jong Lee

    National Cheng Kung University, Taiwan

    5 publications · 142 citations

    5

    h-index

  5. PG
    Patrick Girard

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    5 publications · 91 citations

    5

    h-index

1–5 of 430

Institutions

139

  1. Mentor Technologies

    Tulsa, United States

    10 h-index

    20 publications

    2.2K citations

  2. University of Stuttgart

    Stuttgart, Germany

    7 h-index

    13 publications

    460 citations

  3. Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier

    Montpellier, France

    6 h-index

    21 publications

    647 citations

  4. Siemens (Hungary)

    Budapest, Hungary

    6 h-index

    14 publications

    2.1K citations

  5. Duke University

    Durham, United States

    6 h-index

    8 publications

    167 citations

  6. Intel (United States)

    Santa Clara, United States

    6 h-index

    12 publications

    663 citations

  7. Amrita Vishwa Vidyapeetham

    Coimbatore, India

    5 h-index

    14 publications

    264 citations

  8. IBM (United States)

    Armonk, United States

    5 h-index

    15 publications

    1.9K citations

1–8 of 139

Venues

  1. IEEE Transactions on Computers

    9 publications · 285 citations

    9

    h-index

  2. 8

    h-index

  3. Journal of Electronic Testing

    JETTA · 8 publications · 139 citations

    8

    h-index

  4. IEEE Design & Test of Computers

    5 publications · 410 citations

    5

    h-index

  5. International Test Conference

    Conference · 3 publications · 116 citations

    3

    h-index

1–5