Scan Chain Design
Scan Chain Design is a design methodology in digital integrated circuit testing that integrates sequential logic elements into a shift register structure during test mode to enable controllability and observability of internal circuit states.
641
Publications
25.8K
Citations
1.1K
Authors
276
Institutions
Publications per year
2017–2026
43
641
LFSR-coded test patterns for scan designs
B. Koenemann · Medical Entomology and Zoology · 1991 · 510 citations
Reducing test application time for full scan embedded cores
İlker Hamzaoğlu, J.H. Patel · 2003 · 337 citations
V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations
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Mentor Technologies
Tulsa, United States
27 h-index
113 publications
4.6K citations
University of Iowa
Iowa City, United States
25 h-index
76 publications
4.1K citations
Siemens (Hungary)
Budapest, Hungary
20 h-index
55 publications
3.6K citations
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Montpellier, France
20 h-index
83 publications
3.9K citations
Purdue University West Lafayette
West Lafayette, United States
18 h-index
31 publications
1.2K citations
Synopsys (United States)
Mountain View, United States
17 h-index
51 publications
2.4K citations

Poznań University of Technology
Poznan, Poland
17 h-index
35 publications
1.2K citations

Centre National de la Recherche Scientifique
Paris, France
16 h-index
66 publications
2.7K citations
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46 publications · 2.6K citations
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25 publications · 715 citations
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19 publications · 1.3K citations
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16 publications · 900 citations
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JETTA · 16 publications · 510 citations
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