Scan Chain Design

Scan Chain Design is a design methodology in digital integrated circuit testing that integrates sequential logic elements into a shift register structure during test mode to enable controllability and observability of internal circuit states.

641

Publications

25.8K

Citations

1.1K

Authors

276

Institutions

Publications per year

2017–2026

43

Authors

1.1K

  1. SR
    S.M. Reddy

    University of Iowa, United States

    41 publications · 2.1K citations

    25

    h-index

  2. JR
    Janusz Rajski

    Mentor Technologies, United States

    34 publications · 1.7K citations

    25

    h-index

  3. IP
    Irith Pomeranz

    University of Iowa, United States

    30 publications · 1.5K citations

    20

    h-index

  4. JT
    Jerzy Tyszer

    Poznań University of Technology, Poland

    25 publications · 965 citations

    17

    h-index

  5. KC
    Krishnendu Chakrabarty

    Duke University, United States

    20 publications · 766 citations

    15

    h-index

1–5 of 1.1K

Venues

  1. 26

    h-index

  2. 16

    h-index

  3. IEEE Design & Test of Computers

    19 publications · 1.3K citations

    15

    h-index

  4. IEEE Transactions on Computers

    16 publications · 900 citations

    14

    h-index

  5. Journal of Electronic Testing

    JETTA · 16 publications · 510 citations

    13

    h-index

1–5