2002 · 353 citations · 14 references
EngineeringComputer EngineeringComputer ScienceLow-power DesignMicroelectronicsThermal AnalysisDesign For TestabilityLow-power Digital Circuit DesignPower AnalysisPower ManagementPower OptimizationPower-aware DesignCompactionHeat DissipationLow-power Design For TestabilityScan Chain DesignScan DesignStatic CompactionStatic Power DissipationTest Generation
During scan testing, excessive switching activity can raise average and peak power far above normal operation, leading to heat dissipation and current spike issues, and compacting scan vectors often further increases power to the point of exceeding constraints. The study presents a static compaction procedure to identify a minimal set of scan vectors that satisfies both average and peak power constraints. The authors propose a static compaction algorithm that iteratively merges test cubes to produce a minimal scan vector set meeting the power limits. By carefully ordering test cube merges during static compaction, the authors achieve substantial reductions in both average and peak power, demonstrating a simple, effective method that integrates easily into existing industry test vector generation flows.
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause problems both with heat dissipation and with current spikes. Compacting scan vectors greatly increases the power dissipation for the vectors (generally the power becomes several times greater). The compacted scan vectors often can exceed the power constraints and hence cannot be used. It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced. A static compaction procedure is presented that can be used to find a minimal set of scan vectors that satisfies constraints on both average power and peak power. The proposed approach is simple yet effective and can be easily implemented in the conventional test vector generation flow used in industry today.
14
A distributed BIST control scheme for complex VLSI devices
Y. Zorian · 2002 · 543 citations
Engineering, Computer Engineering, Electrical Engineering +12
V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations