Power Optimization

Power Optimization is an academic concept in the field of Field-Programmable Gate Array research that refers to the systematic reduction of power consumption in reconfigurable digital circuits through architectural, algorithmic, or circuit-level techniques without compromising functional performance or design constraints.

19.8K

Publications

951.8K

Citations

39.8K

Authors

4.2K

Institutions

Publications per year

2017–2026

6K

Authors

39.8K

  1. AP
    Anantha P. Chandrakasan

    Massachusetts Institute of Technology, United States

    84 publications · 15.1K citations

    49

    h-index

  2. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    111 publications · 7.4K citations

    44

    h-index

  3. MP
    Massoud Pedram

    University of Southern California, United States

    124 publications · 6.6K citations

    43

    h-index

  4. DB
    David Blaauw

    University of Michigan, United States

    86 publications · 6.7K citations

    43

    h-index

  5. DW
    Derrick Wing Kwan Ng

    UNSW Sydney, Australia

    70 publications · 8.4K citations

    43

    h-index

1–5 of 39.8K

Venues

  1. IEEE Transactions on Power Systems

    367 publications · 48.5K citations

    110

    h-index

  2. IEEE Transactions on Wireless Communications

    492 publications · 43.5K citations

    101

    h-index

  3. IEEE Journal of Solid-State Circuits

    377 publications · 37.4K citations

    97

    h-index

  4. 87

    h-index

  5. IEEE Transactions on Communications

    316 publications · 23.1K citations

    77

    h-index

1–5