Power Optimization
Power Optimization is an academic concept in the field of Field-Programmable Gate Array research that refers to the systematic reduction of power consumption in reconfigurable digital circuits through architectural, algorithmic, or circuit-level techniques without compromising functional performance or design constraints.
19.8K
Publications
951.8K
Citations
39.8K
Authors
4.2K
Institutions
Publications per year
2017–2026
6K
19.8K
1–5 of 19.8K
39.8K
Massachusetts Institute of Technology, United States
84 publications · 15.1K citations
49
h-index
44
h-index
43
h-index
43
h-index
43
h-index
1–5 of 39.8K
4.2K
Intel (United States)
Santa Clara, United States
73 h-index
1K publications
73.7K citations
Princeton University
Princeton, United States
70 h-index
410 publications
43.5K citations
Tsinghua University
Beijing, China
70 h-index
1.1K publications
53.9K citations

Southeast University
Nanjing, China
67 h-index
675 publications
39.1K citations
Stanford University
Stanford, United States
66 h-index
444 publications
37.1K citations
Massachusetts Institute of Technology
Cambridge, United States
63 h-index
363 publications
34.2K citations
University of Michigan
Ann Arbor, United States
62 h-index
721 publications
46K citations
University of California, Berkeley
Berkeley, United States
61 h-index
402 publications
52K citations
1–8 of 4.2K
367 publications · 48.5K citations
110
h-index
492 publications · 43.5K citations
101
h-index
377 publications · 37.4K citations
97
h-index
495 publications · 29.7K citations
87
h-index
316 publications · 23.1K citations
77
h-index
1–5