Gate-level Power Optimization

Gate-Level Power Optimization is a systematic methodology within electronic design automation that reduces power consumption in digital circuits by modifying gate-level representations through technology-dependent optimizations, timing-aware transformations, and voltage-threshold assignments during the logic synthesis phase.

Publications

3.3K

Citations

252

Authors

100

Institutions

Publications per year

2017–2026

Parents

Power Optimization

Publications

RT-level ITC'99 benchmarks and first ATPG results

Fulvio Corno, M. Sonza Reorda, Giovanni Squillero · IEEE Design & Test of Computers · 2000 · 535 citations

Engineering, Computer Engineering, Computer Science +17

Scaling, power, and the future of CMOS

Mark Horowitz, E. Alon, Dinesh Patil et al. · 2006 · 282 citations

Engineering, Computer Engineering, Electrical Engineering +17

Distributed sleep transistor network for power reduction

Changbo Long, Lei He · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 146 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

Toshinori Sato, Yuji Kunitake · 2007 · 126 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Design and CAD methodologies for low power gate-level monolithic 3D ICs

Shreepad Panth, Kambiz Samadi, Yang Du et al. · 2014 · 120 citations

Engineering, Computer Engineering, Electrical Engineering +16

1–5 of 83

Authors

252

EC
Eduardo Costa
Universidade Católica de Pelotas, Brazil
3 publications · 61 citations
4
h-index
CL
Changbo Long
University of California, Los Angeles, United States
3 publications · 272 citations
3
h-index
AT
Alexander Taubin
Boston University, United States
3 publications · 88 citations
3
h-index
DS
Dennis Sylvester
University of Michigan, United States
3 publications · 127 citations
3
h-index
KJ
Konrad J. Kulikowski
Boston University, United States
3 publications · 88 citations
3
h-index

1–5 of 252

Institutions

100

1–8 of 100

Venues

Integration
4 publications · 57 citations
4
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3 publications · 297 citations
3
h-index
IEEE Access
2 publications · 54 citations
2
h-index
IEEE Transactions on Circuits and Systems for Video Technology
1 publications · 40 citations
2
h-index
International Symposium on Low Power Electronics and Design
Conference · 1 publications · 15 citations
1
h-index

1–5