Scaling, power, and the future of CMOS

TLDR

As systems became more power constrained, optimizing power became critical, and viewing power reduction from an optimization perspective offers valuable insights. The paper reviews the forces driving the power problem, the solutions applied, and the insights these solutions provide. The authors present an optimization framework that surveys low‑power techniques, analyzes variability impacts, and proposes adaptive mechanisms and strategies to mitigate gate‑energy scaling slowdown. The framework demonstrates how variability affects energy cost and identifies adaptive mechanisms and strategies that reduce this cost and address the slowdown in gate‑energy scaling.

Abstract

This paper briefly reviews the forces that caused the power problem, the solutions that were applied, and what the solutions tell us about the problem. As systems became more power constrained, optimizing the power became more critical; viewing power reduction from an optimization perspective provides valuable insights. Section III describes these insights in more detail, including why V/sub dd/ and V/sub th/ have stopped scaling. Section IV describes some of the low power techniques that have been used in the past in the context of the optimization framework. This framework also makes it easy to see the impact of variability, which is discussed in more detail in section V along with the adaptive mechanisms that have been proposed and deployed to minimize the energy cost. Section VI describes possible strategies for dealing with the slowdown in gate energy scaling, and the final section concludes by discussing the implications of these strategies for device designers.