Shreepad Panth - Concepedia

Author

Shreepad Panth

Georgia Institute of Technology ORCID

Also Known As

S. Panth, Shreepad A. Panth, Shreepad Panth

Publications

972

Citations

H-Index

Concepts

All Affiliations

Georgia Institute of Technology Qualcomm (United States)Duke University Hankyong National University Korea Advanced Institute of Science and Technology

About

Shreepad Panth is an author at Georgia Institute of Technology specializing in engineering, computer engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	16	24	936
2	Computer Engineering	15	23	913
3	Computer Science	4	4	212
4	Applied Physics	3	3	139
5	Natural Sciences	2	2	181

Shreepad Panth

Publications

936

Citations

H-Index

Page 1

	Year	Citations
Design and CAD methodologies for low power gate-level monolithic 3D ICs Shreepad Panth, Kambiz Samadi, Yang Du, Transistor-level M3d3D Ic ArchitectureElectrical EngineeringPhysical Design (Electronics)Engineering	2014	118
3D-MAPS: 3D Massively parallel processor with stacked memory Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, EngineeringComputer ArchitectureComputer-aided DesignIntegrated CircuitsMulti-channel Memory Architecture	2012	117
Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs Shreepad Panth, Kambiz Samadi, Yang Du, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsMonolithic 3-D	2017	88
High-density integration of functional modules using monolithic 3D-IC technology Shreepad Panth, Kambiz Samadi, Yang Du, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsInterconnect (Integrated Circuits)	2013	68
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, IEEE Transactions on Computers EngineeringVlsi DesignMemory TierComputer ArchitectureComputer-aided Design	2013	64
Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations Shreepad Panth, Kambiz Samadi, Yang Du, 3D Ic ArchitectureElectrical EngineeringBlock-level Monolithic 3DEngineeringVlsi Design	2014	64
Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs Shreepad Panth, Kambiz Samadi, Yang Du, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 3D Ic ArchitectureElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design	2015	58
Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, EngineeringVlsi DesignComputer ArchitectureMonolithic 3DAccurate Thermal Modeling	2014	57
Design challenges and solutions for ultra-high-density monolithic 3D ICs Shreepad Panth, Sandeep Kumar Samal, Yun Seop Yu, EngineeringComputer ArchitectureMonolithic 3DInterconnect (Integrated Circuits)Monolithic Inter-tier Vias	2014	48
Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVlsi DesignEnergy EfficiencyPackage StructureComputer Architecture	2016	29

Page 1