Low-power Route
A Low-Power Route is a power-aware routing methodology in FPGA design that minimizes dynamic and static power consumption during signal interconnection by optimizing path selection, resource utilization, and switching activity under timing and placement constraints.
11
Publications
914
Citations
30
Authors
13
Institutions
Publications per year
2017–2026
0
11
Problem Statement and Requirements for 6LoWPAN Routing
Carles Gómez, Eunsook Eunah Kim, Dominik Kaspar et al. · 2008 · 33 citations
1–5 of 11
30
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University of Illinois Urbana-Champaign, United States
2 publications · 33 citations
2
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1
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1
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1
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1–5 of 30
13
University of Illinois Urbana-Champaign
Urbana, United States
2 h-index
4 publications
66 citations
Purdue University West Lafayette
West Lafayette, United States
1 h-index
1 publications
21 citations
Twin Cities Orthopedics
Edina, United States
1 h-index
1 publications
18 citations
University of California, Irvine
Irvine, United States
1 h-index
1 publications
18 citations
University of California, Santa Barbara
Santa Barbara, United States
1 h-index
2 publications
36 citations

Universidade Federal de Santa Maria
Santa Maria, Brazil
1 h-index
2 publications
38 citations

Universidade Federal do Paraná
Curitiba, Brazil
1 h-index
1 publications
19 citations

University of Minnesota
Minneapolis, United States
1 h-index
3 publications
54 citations
1–8 of 13
2 publications · 36 citations
2
h-index
1 publications · 32 citations
1
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1 publications · 19 citations
1
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1 publications · 18 citations
1
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1 publications · 21 citations
1
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1–5