Low-power Route

A Low-Power Route is a power-aware routing methodology in FPGA design that minimizes dynamic and static power consumption during signal interconnection by optimizing path selection, resource utilization, and switching activity under timing and placement constraints.

11

Publications

914

Citations

30

Authors

13

Institutions

Publications per year

2017–2026

0

Authors

30

  1. DC
    Deming Chen

    University of Illinois Urbana-Champaign, United States

    2 publications · 33 citations

    2

    h-index

  2. MD
    Martin D. F. Wong

    University of Illinois Urbana-Champaign, United States

    2 publications · 33 citations

    2

    h-index

  3. CB
    Carsten Bormann

    University of Bremen, Germany

    1 publications · 33 citations

    1

    h-index

  4. DK
    Dominik Kaspar

    University of Oslo, Norway

    1 publications · 33 citations

    1

    h-index

  5. WY
    Wen‐Yung Yeh

    Industrial Technology Research Institute, Taiwan

    1 publications · 32 citations

    1

    h-index

1–5 of 30

Venues

  1. 2

    h-index

  2. Nanotechnology

    1 publications · 32 citations

    1

    h-index

  3. Computers & Electrical Engineering

    1 publications · 19 citations

    1

    h-index

  4. 1

    h-index

  5. 1

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1–5