Clock Tree Optimization

Clock Tree Optimization is a circuit design methodology in physical synthesis that specifically addresses the minimization of clock skew, power consumption, and routing resources by constructing an optimal clock distribution network to synchronize sequential elements in a digital integrated circuit.

107

Publications

3.7K

Citations

264

Authors

Institutions

Publications per year

2017–2026

Parents

Power Optimization

Publications

107

Zero skew clock routing with minimum wirelength

Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho et al. · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1992 · 350 citations

Engineering, Computer Engineering, Electrical Engineering +17

Zero-skew clock routing trees with minimum wirelength

Kenneth D. Boese, Andrew B. Kahng · 2003 · 222 citations

Engineering, Computer Engineering, Electrical Engineering +17

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Yannick Bonhomme, Patrick Girard, L. Guiller et al. · 2002 · 141 citations

Engineering, Computer Engineering, Electrical Engineering +17

A modified clock scheme for a low power BIST test pattern generator

Patrick Girard, L. Guiller, C. Landrault et al. · 2002 · 134 citations

Engineering, Computer Engineering, Electrical Engineering +17

Clock-tree power optimization based on RTL clock-gating

Monica Donno, Alessandro Ivaldi, Luca Benini et al. · 2003 · 105 citations

Engineering, Computer Engineering, Computer Science +17

1–5 of 107

Authors

264

SK
Sung Kyu Lim
Georgia Institute of Technology, United States
8 publications · 257 citations
9
h-index
DZ
David Z. Pan
The University of Texas at Austin, United States
6 publications · 187 citations
6
h-index
XZ
Xin Zhao
Georgia Institute of Technology, United States
6 publications · 142 citations
6
h-index
EM
Enrico Macii
Politecnico di Torino, Italy
6 publications · 255 citations
6
h-index
LB
Luca Benini
University of Bologna, Italy
6 publications · 251 citations
6
h-index

1–5 of 264

Institutions

1–8 of 80

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
11 publications · 367 citations
11
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
6 publications · 144 citations
6
h-index
International Conference on Computer Aided Design
Conference · 4 publications · 138 citations
4
h-index
Asia and South Pacific Design Automation Conference
Conference · 3 publications · 77 citations
3
h-index
ACM Transactions on Design Automation of Electronic Systems
TODAES · 3 publications · 64 citations
3
h-index

1–5