C. Landrault

A test vector inhibiting technique for low energy BIST design

Patrick Girard, L. Guiller, C. Landrault et al. · 2003 · 157 citations

Low-power Electronics, Hardware Security, Electrical Engineering +14

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Yannick Bonhomme, Patrick Girard, L. Guiller et al. · 2002 · 140 citations

Engineering, Vlsi Design, Power Optimization (Eda) +17

A modified clock scheme for a low power BIST test pattern generator

Patrick Girard, L. Guiller, C. Landrault et al. · 2002 · 132 citations

Low-power Electronics, Hardware Security, Electrical Engineering +14

Reducing power consumption during test application by test vector ordering

Patrick Girard, C. Landrault, S. Pravossoudovitch et al. · 2002 · 114 citations

Electrical Engineering, Engineering, System Testing +13

Power driven chaining of flip-flops in scan architectures

Yannick Bonhomme, Patrick Girard, C. Landrault et al. · 2003 · 107 citations

Engineering, Vlsi Design, Computer Architecture +16