Yannick Bonhomme

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Yannick Bonhomme, Patrick Girard, L. Guiller et al. · 2002 · 140 citations

Engineering, Vlsi Design, Power Optimization (Eda) +17

Power driven chaining of flip-flops in scan architectures

Yannick Bonhomme, Patrick Girard, C. Landrault et al. · 2003 · 107 citations

Engineering, Vlsi Design, Computer Architecture +16

Design of routing-constrained low power scan chains

Yannick Bonhomme, Patrick Girard, L. Guiller et al. · Design, Automation, and Test in Europe · 2004 · 46 citations

Cluster Computing, Power-aware Computing, Scan-based Architectures +14

An efficient scan tree design for test time reduction

Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara et al. · 2004 · 38 citations

Engineering, Computer Architecture, Software Engineering +20

Generalized parity-check matrices for SEC-DED codes with fixed parity

Valentin Gherman, Samuel Evain, Nathaniel Seymour et al. · 2011 · 28 citations · Full text

Hardware Security, Engineering, Hsiao Parity-check Matrices +14