Interconnect Power Optimization
Interconnect Power Optimization is a design methodology that specifically addresses the reduction of power consumption in on-chip interconnection networks by optimizing physical layout, signaling techniques, and routing strategies, distinguishing it from other power optimization approaches focused on logic or memory components.
297
Publications
12K
Citations
812
Authors
214
Institutions
Publications per year
2017–2026
26
297
1–5 of 297
812
10
h-index
8
h-index
8
h-index
7
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1–5 of 812
214
Georgia Institute of Technology
Atlanta, United States
15 h-index
49 publications
1.5K citations
Intel (United States)
Santa Clara, United States
15 h-index
66 publications
3K citations

Pennsylvania State University
State College, United States
14 h-index
50 publications
3.2K citations
Massachusetts Institute of Technology
Cambridge, United States
14 h-index
27 publications
1.2K citations
University of California, Berkeley
Berkeley, United States
12 h-index
34 publications
2.5K citations
Princeton University
Princeton, United States
12 h-index
25 publications
2.7K citations
University of Michigan
Ann Arbor, United States
10 h-index
29 publications
893 citations
IMEC
Leuven, Belgium
9 h-index
80 publications
2.7K citations
1–8 of 214
20 publications · 1.1K citations
14
h-index
12 publications · 453 citations
12
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6 publications · 295 citations
6
h-index
ICCAD · 5 publications · 129 citations
5
h-index
Conference · 4 publications · 72 citations
4
h-index
1–5