Interconnect Power Optimization

Interconnect Power Optimization is a design methodology that specifically addresses the reduction of power consumption in on-chip interconnection networks by optimizing physical layout, signaling techniques, and routing strategies, distinguishing it from other power optimization approaches focused on logic or memory components.

297

Publications

12K

Citations

812

Authors

214

Institutions

Publications per year

2017–2026

26

Authors

812

  1. JM
    J.D. Meindl

    Georgia Institute of Technology, United States

    10 publications · 255 citations

    10

    h-index

  2. LP
    Li-Shiuan Peh

    Princeton University, United States

    8 publications · 947 citations

    8

    h-index

  3. JA
    Jeffrey A. Davis

    Georgia Institute of Technology, United States

    8 publications · 212 citations

    8

    h-index

  4. LB
    Luca Benini

    University of Bologna, Italy

    7 publications · 502 citations

    7

    h-index

  5. EG
    Eby G. Friedman

    University of Rochester, United States

    7 publications · 240 citations

    7

    h-index

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