Li-Shiuan Peh - Concepedia

Author

Li-Shiuan Peh

Princeton University ORCID

Also Known As

L. Peh, L.-S. Peh, L.S. Peh, Li Shiuan Peh, Li-Shiuan Peh, Li-ShiuanPeh, Li-shiuan Peh, Peh, Li-Shiuan, Shiuan, Peh Li

224

Publications

13.8K

Citations

H-Index

173

Concepts

All Affiliations

Princeton University Massachusetts Institute of Technology National University of Singapore Intel (United States)

About

Li-Shiuan Peh is an author at Princeton University specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	57	121	12.8K
2	Business	4	4	593
3	Arts	1	1	100
4	Language Studies	1	1	23
5	Management	1	1	24

Li-Shiuan Peh

132

Publications

13.3K

Citations

H-Index

Page 1

	Year	Citations
GARNET: A detailed on-chip network model inside a full-system simulator Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Hardware ModelingFlow ControlEngineeringComputer ArchitectureInterconnection Network Architecture	2009	743
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives Radu Mărculescu, Ümit Y. Ogras, Li-Shiuan Peh, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVlsi DesignElectronic DesignComputer ArchitectureResearch Problems	2008	684
Orion: a power-performance simulator for interconnection networks Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, International Symposium on Microarchitecture EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitectureInterconnection Network Architecture	2002	673
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling Chen Sun, Chia-Hsin Owen Chen, George Thomas Kurian, EngineeringDevice IntegrationIntegrated PhotonicsComputer ArchitectureElectrical Technology Scaling	2012	571
A delay model and speculative architecture for pipelined routers Li-Shiuan Peh, William J. Dally Hardware SecurityEngineeringRouter Delay ModelEdge ComputingRouter Architecture	2002	544
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration Andrew B. Kahng, Bin Li, Li-Shiuan Peh, EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitectureNoc Power	2009	531
Dynamic voltage scaling with links for power optimization of interconnection networks Li Shang, Li-Shiuan Peh, Niraj K. Jha EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitectureNetwork Analysis	2003	452
Research Challenges for On-Chip Interconnection Networks John D. Owens, William J. Dally, R. Ho, IEEE Micro Hardware SecuritySystem On ChipEngineeringOcin TechnologyOn-chip Interconnection Networks	2007	393
Research Challenges for On-Chip Interconnection Networks John D. Owens, William J. Dally, R. Ho, IEEE Micro Hardware SecuritySystem On ChipEngineeringOcin TechnologyOn-chip Interconnection Networks	2007	343
Power-driven design of router microarchitectures in on-chip networks Hangsheng Wang, Li-Shiuan Peh, Sharad Malik International Symposium on Microarchitecture Hardware SecurityRouter MicroarchitecturesEngineeringPrior MicroarchitecturesEdge Computing	2003	342

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