DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling

TLDR

Many‑core chips demand high bandwidth, prompting investigation of integrated photonic links as a promising alternative to traditional electrical interconnects, yet existing evaluations rely on simplifications that underscore the need for an accurate modeling tool. This paper introduces DSENT, a NoC modeling tool designed for rapid design‑space exploration of electrical and opto‑electrical networks. DSENT’s framework is explained and an energy‑driven case study is performed, concentrating on electrical technology scaling, photonic parameters, and thermal tuning. Results reveal that different technology scenarios impact performance and emphasize the necessity of reducing laser and thermal tuning power in photonic networks, as these consumptions are non‑data‑dependent.

Abstract

With the rise of many-core chips that require substantial bandwidth from the network on chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects. While numerous opto-electronic NoCs have been proposed, evaluations of photonic architectures have thus-far had to use a number of simplifications, reflecting the need for a modeling tool that accurately captures the tradeoffs for the emerging technology and its impacts on the overall network. In this paper, we present DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks. We explain our modeling framework and perform an energy-driven case study, focusing on electrical technology scaling, photonic parameters, and thermal tuning. Our results show the implications of different technology scenarios and, in particular, the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.