Chip-scale Packaging
Chip-Scale Packaging is a type of integrated circuit packaging technology that encapsulates a semiconductor chip with dimensions no greater than 1.2 times the size of the die itself, enabling minimal footprint integration while maintaining direct interconnection and protection comparable to traditional packaging.
371
Publications
11.7K
Citations
1.4K
Authors
284
Institutions
Publications per year
2017–2026
56
371
1–5 of 371
1.4K
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284
Advanced Semiconductor Engineering (Taiwan)
Kaohsiung, Taiwan
14 h-index
74 publications
1.9K citations
National Tsing Hua University
Hsinchu, Taiwan
13 h-index
50 publications
1.4K citations
Amkor Technology (United States)
Tempe, United States
13 h-index
63 publications
2.7K citations
Texas Instruments (United States)
Dallas, United States
11 h-index
33 publications
827 citations
Georgia Institute of Technology
Atlanta, United States
10 h-index
34 publications
555 citations
Motorola (United States)
Schaumburg, United States
10 h-index
32 publications
547 citations
Taiwan Semiconductor Manufacturing Company (Taiwan)
Hsinchu, Taiwan
9 h-index
36 publications
1.1K citations
Binghamton University
Binghamton, United States
9 h-index
30 publications
687 citations
1–8 of 284
20 publications · 1.4K citations
17
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20 publications · 692 citations
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18 publications · 476 citations
13
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11 publications · 287 citations
11
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11 publications · 352 citations
10
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