Chip-scale Packaging

Chip-Scale Packaging is a type of integrated circuit packaging technology that encapsulates a semiconductor chip with dimensions no greater than 1.2 times the size of the die itself, enabling minimal footprint integration while maintaining direct interconnection and protection comparable to traditional packaging.

371

Publications

11.7K

Citations

1.4K

Authors

284

Institutions

Publications per year

2017–2026

56

Authors

1.4K

  1. KC
    Kuo‐Ning Chiang

    National Tsing Hua University, Taiwan

    17 publications · 479 citations

    13

    h-index

  2. YL
    Yi‐Shao Lai

    Advanced Semiconductor Engineering (Taiwan), Taiwan

    16 publications · 467 citations

    12

    h-index

  3. XF
    Xuejun Fan

    Lamar University, United States

    11 publications · 266 citations

    11

    h-index

  4. JH
    John H. Lau

    Industrial Technology Research Institute, Taiwan

    10 publications · 839 citations

    10

    h-index

  5. LN
    Luu Nguyen

    Texas Instruments (United States), United States

    10 publications · 701 citations

    10

    h-index

1–5 of 1.4K

Venues

  1. Microelectronics Reliability

    20 publications · 1.4K citations

    17

    h-index

  2. IEEE Transactions on Advanced Packaging

    20 publications · 692 citations

    14

    h-index

  3. Journal of Electronic Packaging

    18 publications · 476 citations

    13

    h-index

  4. 11

    h-index

  5. 10

    h-index

1–5