Recent Advances and Trends in Advanced Packaging

TLDR

The study defines advanced packaging and examines chiplet design and heterogeneous integration as alternatives to system‑on‑chip solutions for advanced nodes. The authors classify advanced packaging into 2‑D, 2.1‑D, 2.3‑D, 2.5‑D, and 3‑D IC integration, evaluate substrate characteristics, lateral communication methods, fan‑in and fan‑out packaging variants, low‑loss dielectric materials, and assembly techniques such as mass reflow, thermocompression, and bumpless hybrid bonding.

Abstract

In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.