Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

Impact life prediction modeling of TFBGA packages under board level drop test

Tong Yan Tee, Hun Shen Ng, Chwee Teck Lim et al. · Microelectronics Reliability · 2004 · 192 citations

Architecture, Computer Engineering, Packaging Design +11

Ductile-to-brittle transition in Sn–Zn solder joints measured by impact test

Munehiro Date, T. Shoji, M. Fujiyoshi et al. · Scripta Materialia · 2004 · 162 citations

Natural Sciences, Materials Engineering, Materials Science +16

Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact

Tong Yan Tee, Jing-en Luan, E. Pek et al. · 2004 · 160 citations

Engineering, Electrical Engineering, Materials Engineering +17

Modal analysis and dynamic responses of board level drop test

Jing-en Luan, Tong Yan Tee, E. Pek et al. · 2004 · 90 citations

Natural Sciences, Electrical Engineering, Materials Science +17

Support excitation scheme for transient analysis of JEDEC board-level drop test

Chang-Lin Yeh, Yi‐Shao Lai · Microelectronics Reliability · 2005 · 88 citations

Engineering, Electrical Engineering, Microelectronics +9