6Å EOT Si<inf>0.45</inf>Ge<inf>0.55</inf> pMOSFET with optimized reliability (V<inf>DD</inf>=1V): Meeting the NBTI lifetime target at ultra-thin EOT

Abstract

6Å EOT Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.45</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</sub> pFETs with 10 year lifetime at operating conditions (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1V) are demonstrated. Ultra-thin EOT is achieved by interfacial layer (IL) scavenging. Negative Bias Temperature Instability (NBTI) is alleviated using a high Ge fraction, a thick SiGe quantum well (QW) and a thin Si cap. Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB) are shown also to not constitute a showstopper for optimized SiGe devices.