M. Denais - Concepedia

Author

M. Denais

STMicroelectronics (France)

Also Known As

Denais, Martin, M Denais, M. Denais, Martin Denais

Publications

2.1K

Citations

H-Index

Concepts

All Affiliations

STMicroelectronics (France)Centre National de la Recherche Scientifique Philips (France)Institut des Sciences de l'Evolution de Montpellier Institut Supérieur de l'Électronique et du Numérique

About

M. Denais is an author at STMicroelectronics (France) specializing in engineering, applied physics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	16	24	2K
2	Applied Physics	15	18	1.8K
3	Electrical Engineering	15	19	1.4K
4	Computer Engineering	5	5	113
5	Medicine	1	1	38

M. Denais

Publications

Citations

H-Index

Page 1

	Year	Citations
Review on high-k dielectrics reliability issues G. Ribes, Jérôme Mitard, M. Denais, IEEE Transactions on Device and Materials Reliability DielectricsEngineeringSemiconductor DeviceHigh-k MaterialsNanoelectronics	2005	519
NBTI degradation: From physical mechanisms to modelling V. Huard, M. Denais, C. Parthasarathy Microelectronics Reliability EngineeringPhysicsBias Temperature InstabilityApplied PhysicsTime-dependent Dielectric Breakdown	2005	498
On-the-flycharacterization of NBTI in ultra-tihin gate oxide PMOSFET's M. Denais, A. Bravaix, V. Huard, Electrical EngineeringUltra-tihin GateEngineeringSemiconductor DevicePhysics	2005	234
A thorough investigation of MOSFETs NBTI degradation V. Huard, M. Denais, F. Perrier, Microelectronics Reliability Electrical EngineeringEngineeringBias Temperature InstabilityMosfets Nbti DegradationCircuit Reliability	2004	147
Interface Trap Generation and Hole Trapping Under NBTI and PBTI in Advanced CMOS Technology With a 2-nm Gate Oxide M. Denais, V. Huard, C. Parthasarathy, IEEE Transactions on Device and Materials Reliability Electrical EngineeringEngineeringAdvanced Cmos TechnologyNanoelectronicsElectronic Engineering	2004	122
Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors V. Huard, M. Denais Device ModelingPmos TransistorsElectrical EngineeringAdequate MethodologyTransient Effect	2004	119
New Insights into Recovery Characteristics Post NBTI Stress CR Parthasarathy, M. Denais, V. Huard, Materials EngineeringStress BiasNbti DegradationEngineeringPhysics	2006	38
Physical Modeling of Negative Bias Temperature Instabilities for Predictive Extrapolation V. Huard, C. Parthasarathy, C. Guérin, EngineeringSemiconductor DeviceUncertainty QuantificationPhysical ModelingNumerical Simulation	2006	33
Paradigm Shift for NBTI Characterization in Ultra-Scaled CMOS Technologies M. Denais, A. Bravaix, V. Huard, EngineeringVlsi DesignAc Nbti CasePower ElectronicsReliability Engineering	2006	31
Designing in reliability in advanced CMOS technologies C. Parthasarathy, M. Denais, V. Huard, Microelectronics Reliability ReliabilityReliability EngineeringEngineeringHardware ReliabilityAdvanced Cmos Technologies	2006	29

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