C. Parthasarathy - Concepedia

Author

C. Parthasarathy

Also Known As

C Parthasarathy, C. Parthasarathy, C. R. Parthasarathy, C.R. Parthasarathy, CHITRA RAJALAKSHMI PARTHASARATHY, Chibibharath Parthasarathy, Nazeeya Anjum, Parthasarathy, C. R.

Publications

Citations

H-Index

Concepts

All Affiliations

STMicroelectronics (France)Centre National de la Recherche Scientifique Philips (France)Institut des Matériaux, de Microélectronique et des Nanosciences de Provence STMicroelectronics (India)

About

C. Parthasarathy is an author at STMicroelectronics (France) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	19	1.8K
2	Applied Physics	11	11	1.4K
3	Computer Engineering	8	8	401
4	Education	1	1	14
5	Civil Engineering	1	1	14

C. Parthasarathy

Publications

1.8K

Citations

H-Index

Page 1

	Year	Citations
Review on high-k dielectrics reliability issues G. Ribes, Jérôme Mitard, M. Denais, IEEE Transactions on Device and Materials Reliability DielectricsEngineeringSemiconductor DeviceHigh-k MaterialsNanoelectronics	2005	519
NBTI degradation: From physical mechanisms to modelling V. Huard, M. Denais, C. Parthasarathy Microelectronics Reliability EngineeringPhysicsBias Temperature InstabilityApplied PhysicsTime-dependent Dielectric Breakdown	2005	498
A thorough investigation of MOSFETs NBTI degradation V. Huard, M. Denais, F. Perrier, Microelectronics Reliability Electrical EngineeringEngineeringBias Temperature InstabilityMosfets Nbti DegradationCircuit Reliability	2004	147
NBTI degradation: From transistor to SRAM arrays V. Huard, C. Parthasarathy, C. Guérin, Device ModelingSram BitcellElectrical EngineeringEngineeringVlsi Design	2008	146
Interface Trap Generation and Hole Trapping Under NBTI and PBTI in Advanced CMOS Technology With a 2-nm Gate Oxide M. Denais, V. Huard, C. Parthasarathy, IEEE Transactions on Device and Materials Reliability Electrical EngineeringEngineeringAdvanced Cmos TechnologyNanoelectronicsElectronic Engineering	2004	122
New characterization and modeling approach for NBTI degradation from transistor to product level V. Huard, C. Parthasarathy, N. Rallet, Device ModelingElectrical EngineeringProduct LevelEngineeringPhysical Design (Electronics)	2007	95
Design-in-Reliability Approach for NBTI and Hot-Carrier Degradations in Advanced Nodes Vincent Huard, C. Parthasarathy, A. Bravaix, IEEE Transactions on Device and Materials Reliability EngineeringIntegrated CircuitsReliability EngineeringNanoelectronicsModeling And Simulation	2007	44
Physical Modeling of Negative Bias Temperature Instabilities for Predictive Extrapolation V. Huard, C. Parthasarathy, C. Guérin, EngineeringSemiconductor DeviceUncertainty QuantificationPhysical ModelingNumerical Simulation	2006	33
Paradigm Shift for NBTI Characterization in Ultra-Scaled CMOS Technologies M. Denais, A. Bravaix, V. Huard, EngineeringVlsi DesignAc Nbti CasePower ElectronicsReliability Engineering	2006	31
A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform F. Arnaud, F. Salvetti, D. Lenoble, Low PowerElectrical EngineeringEngineeringVlsi DesignBeam Lithography	2004	30

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