2012 · 41 citations · 16 references
EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesChip PackagingIntegrated Circuit DesignIntegrated Circuit DevicesInterconnect TechnologySemiconductor InterfacesVery-large-scale Integration Layout3D Integrated CircuitsElectromigrationElectromigration AnalysisThree-dimensional Integrated Circuit InterconnectsThree-dimensional Integrated Circuit LayoutThree-dimensional IntegrationThrough-silicon ViasVoid Nucleation
The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances.
16
Electromigration path in Cu thin-film lines
C.‐K. Hu, R. Rosenberg, K. Y. Lee · Applied Physics Letters · 1999 · 329 citations
Natural Sciences, Materials Engineering, Materials Science +17
Resistance increase due to electromigration induced depletion under TSV
Thomas Frank, C. Chappaz, Philip R. LeDuc et al. · 2011 · 73 citations