Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

D.K. Schroder, Jeff A. Babcock · Journal of Applied Physics · 2003 · 1K citations

Engineering, Electrical Engineering, Physics +17

Simple technique for separating the effects of interface traps and trapped-oxide charge in metal-oxide-semiconductor transistors

P. J. McWhorter, P.S. Winokur · Applied Physics Letters · 1986 · 774 citations · Full text

Engineering, Electrical Engineering, Microelectronics +16

Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

Kjell Jeppson, Christer Svensson · Journal of Applied Physics · 1977 · 678 citations · Full text

Engineering, Electrical Engineering, Materials Science +14

NBTI degradation: From physical mechanisms to modelling

V. Huard, M. Denais, C. Parthasarathy · Microelectronics Reliability · 2005 · 503 citations

Engineering, Electrical Engineering, Electronic Materials +10

Interface-trap generation at ultrathin SiO2 (4–6 nm)-Si interfaces during negative-bias temperature aging

Shigeo Ogawa, Masakazu Shimaya, Noboru Shiono · Journal of Applied Physics · 1995 · 198 citations

Engineering, Materials Engineering, Materials Science +17