Interface-trap generation at ultrathin SiO2 (4–6 nm)-Si interfaces during negative-bias temperature aging

Abstract

This article reports an investigation of the negative-bias temperature instability in metal-oxide-silicon (MOS) systems with gate oxide thickness (Tox) in the range of 4.2–30 nm. The bias temperature aging was performed on p-type samples with applied negative oxide fields (1.6–5.0 MV/cm) over a temperature range of 150–290 °C. The maximum aging time was 5000 h. The interface-trap distribution was evaluated by the conductance technique. This time-consuming method yields reliable results even in ultrathin oxides, if appropriate corrections are made. The interface-trap generation and the concurrent fixed oxide charge can be expressed by simple empirical expressions. Their characteristic features are the inverse proportionality to oxide thickness (Tox) for the generated interface-trap density (Nit) and no thickness dependence for the fixed charge generation. A general phenomenological model is proposed to explain these empirical expressions in terms of the diffusion-reaction chemistry between hydrogenated trivalent silicon and the diffusing species. It is developed for the uncharged (neutral) and positively charged cases of diffusing species. Experimental results support the neutral-species (molecular hydrogen) model and the observed T−1ox dependence of Nit generation implies that the negative-bias temperature instability becomes more severe for ultrathin gate oxide MOS devices.