Microelectronic Engineering · 2016 · 12 citations · 5 references
3D Ic ArchitectureElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)MicrofabricationMicron DiameterApplied PhysicsSilicon ViasDielectric Liner ReliabilityElectronic PackagingDevice ReliabilityMicroelectronicsSilicon On InsulatorElectrical Insulation
5
Impact of barrier integrity on liner reliability in 3D through silicon vias
Yunlong Li, Yann Civale, Yoshiyuki Oba et al. · 2013 · 12 citations
Engineering, Pvd Ti, Silicon Vias +16