Sarasvathi Thangaraju

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

A. Mercha, Geert Van der Plas, Victor Moroz et al. · 2010 · 119 citations

Engineering, Computer Engineering, Electrical Engineering +17

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

Anne Jourdain, Thibault Buisson, Alain Phommahaxay et al. · 2011 · 55 citations

Engineering, Electrical Engineering, Microelectronics +16

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

A. Redolfi, Dimitrios Velenis, Sarasvathi Thangaraju et al. · 2011 · 52 citations

Engineering, Electrical Engineering, Manufacturing Processes +14

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

A. Wei, Jagar Singh, G. Bouche et al. · 2014 · 17 citations

Engineering, Electrical Engineering, Materials Science +17

Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology

Mohamed A. Rabie, C.S. Premachandran, Rakesh Ranjan et al. · 2014 · 16 citations

Engineering, Electrical Engineering, Microelectronics +14