Victor Moroz

Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV)

Aditya P. Karmarkar, Xiaopeng Xu, Victor Moroz · 2009 · 128 citations

Engineering, 3D-integration Structures, Mechanical Engineering +23

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

A. Mercha, Geert Van der Plas, Victor Moroz et al. · 2010 · 119 citations

Engineering, Stress Aware Design, Mechanical Engineering +22

7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn

Suyog Gupta, Victor Moroz, Lee Smith et al. · IEEE Transactions on Electron Devices · 2014 · 97 citations

Materials Engineering, Electrical Engineering, Engineering +14

pMOSFET with 200% mobility enhancement induced by multiple stressors

L. Washington, F. Nouri, S. Thirupapuliyur et al. · IEEE Electron Device Letters · 2006 · 68 citations

Materials Engineering, Electrical Engineering, Engineering +15

Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

Xin Sun, Qiang Lü, Victor Moroz et al. · IEEE Electron Device Letters · 2008 · 68 citations

3D Ic Architecture, Electrical Engineering, Cmos Scaling +12