Lee Smith

7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn

Suyog Gupta, Victor Moroz, Lee Smith et al. · IEEE Transactions on Electron Devices · 2014 · 97 citations

Materials Engineering, Electrical Engineering, Engineering +14

pMOSFET with 200% mobility enhancement induced by multiple stressors

L. Washington, F. Nouri, S. Thirupapuliyur et al. · IEEE Electron Device Letters · 2006 · 68 citations

Materials Engineering, Electrical Engineering, Engineering +15

Exploring the limits of stress-enhanced hole mobility

Lee Smith, Victor Moroz, Geert Eneman et al. · IEEE Electron Device Letters · 2005 · 61 citations

Engineering, Residual Stress, Semiconductor Device +17

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

Geert Eneman, Peter Verheyen, R. Rooyackers et al. · IEEE Transactions on Electron Devices · 2006 · 56 citations

Device Modeling, Electrical Engineering, Engineering +15

Application of through mold via (TMV) as PoP base package

Jinseong Kim, Kiwook Lee, Dongjoo Park et al. · 2008 · 53 citations

Mold Control, 3D Ic Architecture, Chip-scale Package +13