R. Rooyackers

Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET

A. Walke, A. Vandooren, R. Rooyackers et al. · IEEE Transactions on Electron Devices · 2014 · 144 citations

Trap-assisted Tunneling, Engineering, Integrated Circuits +16

Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs

A. Vandooren, Daniele Leonelli, R. Rooyackers et al. · Solid-State Electronics · 2013 · 140 citations

Trap-assisted Tunneling, Electrical Engineering, Sige Hetero-junction Tunnel-fets +9

Impact of Line-Edge Roughness on FinFET Matching Performance

Emanuele Baravelli, Abhisek Dixit, R. Rooyackers et al. · IEEE Transactions on Electron Devices · 2007 · 139 citations

Hardware Security, Finfet Matching Performance, Electrical Engineering +14

Drain voltage dependent analytical model of tunnel field-effect transistors

Anne S. Verhulst, Daniele Leonelli, R. Rooyackers et al. · Journal of Applied Physics · 2011 · 123 citations

Device Modeling, Electrical Engineering, Tfet Performance +11

Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source

F. S. Neves, Paula Ghedini Der Agopian, João Antônio Martino et al. · IEEE Transactions on Electron Devices · 2016 · 119 citations