Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs

Abhisek Dixit, Anil Kottantharayil, Nadine Collaert, +1

IEEE Transactions on Electron Devices

Device ModelingElectrical EngineeringSelective Epitaxial GrowthEngineeringNanoelectronics +8

Impact of Line-Edge Roughness on FinFET Matching Performance

Emanuele Baravelli, Abhisek Dixit, R. Rooyackers, +3

IEEE Transactions on Electron Devices

Hardware SecurityFinfet Matching PerformanceElectrical EngineeringRdf PatterningEngineering +12

Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance

Emanuele Baravelli, M. Jurczak, N. Speciale, +2

IEEE Transactions on Nanotechnology

Device ModelingRandom Dopant FluctuationsElectrical EngineeringFinfet Matching PerformanceEngineering +10

FinFET analogue characterization from DC to 110GHz

Dimitri Lederer, Valeriya Kilchytska, Tamara Rudenko, +5

Solid-State Electronics

Electrical EngineeringFinfet Analogue CharacterizationEngineeringHigh-frequency DeviceNanoelectronics +4

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

K. von Arnim, E. Augendre, A.C. Pacha, +15

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignMixed-signal Integrated Circuit +9

Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET

Ramendra Singh, Kritika Aditya, Shivendra Singh Parihar, +4

IEEE Electron Device Letters

Magnetic PropertiesEngineeringMagnetic MaterialsBase FinfetNegative Capacitance Finfet +14

Multi-gate devices for the 32nm technology node and beyond

Nadine Collaert, A. De Keersgieter, Abhisek Dixit, +17

Planar Bulk DevicesElectrical EngineeringEngineeringVlsi DesignHigh-speed Electronics +13

Multi-gate devices for the 32nm technology node and beyond

Nadine Collaert, A. De Keersgieter, Abhisek Dixit, +17

Solid-State Electronics

Electrical EngineeringEngineeringVlsi DesignNanoelectronicsComputer Engineering +5

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Ishita Jain, Anshul Gupta, Terence B. Hook, +1

IEEE Transactions on Electron Devices

EngineeringThermal ConductivityEffective Thermal ResistancePhysical Design (Electronics)Nanoelectronics +21

Reliability Comparison of Triple-Gate Versus Planar SOI FETs

Felice Crupi, B. Kaczer, R. Degraeve, +6

IEEE Transactions on Electron Devices

EngineeringSemiconductor DeviceReliability EngineeringNanoelectronicsElectronic Engineering +14