K. von Arnim

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

K. von Arnim, E. Augendre, A.C. Pacha et al. · 2007 · 76 citations

Low-power Electronics, Electrical Engineering, Engineering +11

Multi-gate devices for the 32nm technology node and beyond

Nadine Collaert, A. De Keersgieter, Abhisek Dixit et al. · 2007 · 60 citations

Planar Bulk Devices, Electrical Engineering, Engineering +15

Multi-gate devices for the 32nm technology node and beyond

Nadine Collaert, A. De Keersgieter, Abhisek Dixit et al. · Solid-State Electronics · 2008 · 57 citations

Electrical Engineering, Engineering, Vlsi Design +7

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

K. von Arnim, E. Borinski, P. Seegebrecht et al. · IEEE Journal of Solid-State Circuits · 2005 · 56 citations

Low-power Electronics, Electrical Engineering, Low-power Digital Circuits +12

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

C. Pacha, B. Martin, K. von Arnim et al. · 2004 · 53 citations

Device Modeling, Threshold Voltage Model, Electrical Engineering +15