C. Pacha

Threshold logic circuit design of parallel adders using resonant tunneling devices

C. Pacha, U. Auer, C. Burwick et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2000 · 137 citations

Parallel Adders, Electrical Engineering, Threshold Logic Gates +13

Aspects of systems and circuits for nanoelectronics

K. Goser, C. Pacha, Andreas Kanstein et al. · Proceedings of the IEEE · 1997 · 80 citations

Electrical Engineering, Engineering, Quantum Computing +12

The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

T. Nirschl, Pengzhan Wang, C. E. Webe et al. · 2005 · 70 citations

Electrical Engineering, Engineering, Vlsi Design +11

Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes

W. Prost, U. Auer, F.‐J. Tegude et al. · International Journal of Circuit Theory and Applications · 2000 · 57 citations

Engineering, Vlsi Design, Rtd Peak Voltage +21

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

K. von Arnim, E. Borinski, P. Seegebrecht et al. · IEEE Journal of Solid-State Circuits · 2005 · 56 citations

Low-power Electronics, Electrical Engineering, Low-power Digital Circuits +12