Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

Abstract

A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).