Alain Phommahaxay

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Vlsi Design, 3-D Chip Stacks +17

Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

Eric Beyne, Soon-Wook Kim, Lan Peng et al. · 2017 · 130 citations

Engineering, Integrated Circuits, Silicon On Insulator +16

Cu/Sn microbumps interconnect for 3D TSV chip stacking

Rahul Agarwal, Wenqi Zhang, Paresh Limaye et al. · 2010 · 96 citations

Engineering, Mechanical Engineering, Computer Architecture +17

2D materials: roadmap to CMOS integration

Cedric Huyghebaert, T. Schram, Quentin Smets et al. · 2018 · 94 citations

Engineering, Device Integration, Low Dimensional Material +17

Influence of Composition of SiCN as Interfacial Layer on Plasma Activated Direct Bonding

Fumihiro Inoue, Lan Peng, Serena Iacovo et al. · ECS Journal of Solid State Science and Technology · 2019 · 68 citations · Full text