Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi, +34

IEEE Journal of Solid-State Circuits

EngineeringVlsi Design3-D Chip StacksComputer ArchitectureDesign Issues +15

Cu/Sn microbumps interconnect for 3D TSV chip stacking

Rahul Agarwal, Wenqi Zhang, Paresh Limaye, +4

EngineeringMechanical EngineeringComputer ArchitectureInterconnect (Integrated Circuits)Low Temperature Stacking +15

Design issues and considerations for low-cost 3D TSV IC technology

Geert Van der Plas, Paresh Limaye, A. Mercha, +31

EngineeringVlsi DesignComputer ArchitectureKey Design IssuesThermal Hot Spots +14

Number theory in digital signal processing

Rahul Agarwal

IEEE Transactions on Acoustics Speech and Signal Processing

Signal ProcessingComputational Number TheoryReal Data TypeResidue System

High density Cu-Sn TLP bonding for 3D integration

Rahul Agarwal, Wenqi Zhang, Paresh Limaye, +1

EngineeringMechanical EngineeringInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)Electronic Packaging +14

Fabrication of vertical mirrors using plasma etch and KOH:IPA polishing

Rahul Agarwal, Scott Samson, Shekhar Bhansali

Journal of Micromechanics and Microengineering

EngineeringIntegrated CircuitsVertical MirrorsSilicon On InsulatorPlasma Processing +14

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping

Yann Civale, Deniz Sabuncuoglu Tezcan, Harold Philipsen, +6

Engineering3D-wlp Tsv FlowInterconnect (Integrated Circuits)Temporary CarriersWafer Scale Processing +18

Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application

Frank Kuechenmeister, D. Breuer, H. Geisler, +5

EngineeringFhis PaperIndustrial EngineeringMechanical StabilityComputer Architecture +14

Insertion bonding: A novel Cu-Cu bonding approach for 3D integration

Chukwudi Okoro, Rahul Agarwal, Paresh Limaye, +3

EngineeringInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)Electronic Packaging +19

Substrate integrated waveguide based cavity‐backed self‐triplexing slot antenna for X‐Ku band applications

Padmini Nigam, Rahul Agarwal, Arjuna Muduli, +2

International Journal of RF and Microwave Computer-Aided Engineering

Siw CavityRadiated Quarter CavitiesEngineeringAntennaX‐ku Band Applications +5