Rahul Agarwal

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Vlsi Design, 3-D Chip Stacks +17

Cu/Sn microbumps interconnect for 3D TSV chip stacking

Rahul Agarwal, Wenqi Zhang, Paresh Limaye et al. · 2010 · 96 citations

Engineering, Mechanical Engineering, Computer Architecture +17

Design issues and considerations for low-cost 3D TSV IC technology

Geert Van der Plas, Paresh Limaye, A. Mercha et al. · 2010 · 61 citations

Engineering, Vlsi Design, Computer Architecture +16

Number theory in digital signal processing

Rahul Agarwal · IEEE Transactions on Acoustics Speech and Signal Processing · 1980 · 48 citations

Signal Processing, Computational Number Theory, Real Data Type +1

High density Cu-Sn TLP bonding for 3D integration

Rahul Agarwal, Wenqi Zhang, Paresh Limaye et al. · 2009 · 36 citations

Engineering, Mechanical Engineering, Interconnect (Integrated Circuits) +16