Paresh Limaye

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Vlsi Design, 3-D Chip Stacks +17

Thermal cycling reliability of SnAgCu and SnPb solder joints: A comparison for several IC-packages

Bart Vandevelde, Mario González, Paresh Limaye et al. · Microelectronics Reliability · 2006 · 120 citations

Electrical Engineering, Chip-scale Package, Engineering +10

Cu/Sn microbumps interconnect for 3D TSV chip stacking

Rahul Agarwal, Wenqi Zhang, Paresh Limaye et al. · 2010 · 96 citations

Engineering, Mechanical Engineering, Computer Architecture +17

Design issues and considerations for low-cost 3D TSV IC technology

Geert Van der Plas, Paresh Limaye, A. Mercha et al. · 2010 · 61 citations

Engineering, Vlsi Design, Computer Architecture +16

Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking

Riet Labie, Paresh Limaye, C.J. Berry et al. · 2010 · 60 citations

Engineering, Cu-sn Imc Bumps, Integrated Circuits +16