Mohamed A. Rabie

A kinetic model for the oxidation of silicon germanium alloys

Mohamed A. Rabie, Yaser M. Haddara, Jacques Carette · Journal of Applied Physics · 2005 · 43 citations

Engineering, Oxidation Resistance, Silicon On Insulator +17

Process Development and Optimization for 3 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

Dingyou Zhang, Daniel M. Smith, Gopal Kumarapuram et al. · IEEE Transactions on Semiconductor Manufacturing · 2015 · 21 citations

Engineering, Process Development, Dielectric Liner Coverage +16

TSV residual Cu step height analysis by white light interferometry for 3D integration

Daniel M. Smith, Sanjeev Singh, Yudesh Ramnath et al. · 2015 · 20 citations

Electrical Engineering, Engineering, Advanced Packaging (Semiconductors) +11

Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology

Mohamed A. Rabie, C.S. Premachandran, Rakesh Ranjan et al. · 2014 · 16 citations

Stack Process Development, Electrical Engineering, Engineering +12

Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level

Sarasvathi Thangaraju, Luke England, Mohamed A. Rabie et al. · 2014 · 12 citations

3D Ic Architecture, Electrical Engineering, Chip-scale Package +14