Dimitrios Velenis

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Vlsi Design, 3-D Chip Stacks +17

Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

Eric Beyne, Soon-Wook Kim, Lan Peng et al. · 2017 · 130 citations

Engineering, Integrated Circuits, Silicon On Insulator +16

Impact of 3D design choices on manufacturing cost

Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen et al. · 2009 · 97 citations

Engineering, Computer Architecture, Cost Model +21

Design issues and considerations for low-cost 3D TSV IC technology

Geert Van der Plas, Paresh Limaye, A. Mercha et al. · 2010 · 61 citations

Engineering, Vlsi Design, Computer Architecture +16

Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process

Soon-Wook Kim, Mikael Detalle, Lan Peng et al. · 2016 · 57 citations

Engineering, Integrated Circuits, Interconnect (Integrated Circuits) +20