2007 · 15 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ScalingIntegrated Circuit DesignMemory Subsystem DesignPhysical DesignVery-large-scale Integration LayoutGate Oxide ScalingGate OxidesGate Stack EngineeringMetal GatesNoise Margin AnalysisNoise MarginsStatic Noise MarginStatic Random-access Memory Design
We present an investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static noise margins (SNM) of 210 mV have been measured at IV VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.
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Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici et al. · 2005 · 156 citations
Engineering, Computer Engineering, Electrical Engineering +17