Noise Margin Analysis

Noise Margin Analysis is a metric-based method in electronic circuit design that quantifies the tolerance of a logic circuit to undesired voltage fluctuations by determining the difference between the actual signal levels and the minimum acceptable thresholds for correct logical operation, particularly under near-threshold and subthreshold operating conditions where signal integrity is highly sensitive to process, voltage, and temperature variations.

161

Publications

7.6K

Citations

571

Authors

159

Institutions

Publications per year

2017–2026

18

Authors

571

  1. SM
    Subhasish Mitra

    Stanford University, United States

    5 publications · 188 citations

    5

    h-index

  2. TH
    Toshiro Hiramoto

    The University of Tokyo, Japan

    5 publications · 150 citations

    5

    h-index

  3. SK
    Shiro Kamohara

    The University of Tokyo, Japan

    4 publications · 140 citations

    4

    h-index

  4. TS
    Takuya Saraya

    The University of Tokyo, Japan

    4 publications · 140 citations

    4

    h-index

  5. MA
    Massimo Alioto

    National University of Singapore, Singapore

    4 publications · 94 citations

    4

    h-index

1–5 of 571

Venues

  1. IEEE Transactions on Electron Devices

    19 publications · 769 citations

    15

    h-index

  2. IEEE Journal of Solid-State Circuits

    13 publications · 1.1K citations

    12

    h-index

  3. IEEE Electron Device Letters

    10 publications · 573 citations

    10

    h-index

  4. 5

    h-index

  5. 4

    h-index

1–5