Static Noise Margin
Static Noise Margin is a metric in standard cell design that quantifies the maximum tolerable static noise voltage a logic gate can withstand without erroneous switching, distinguishing it from dynamic or transient noise measures by evaluating steady-state circuit stability.
373
Publications
14.9K
Citations
1.5K
Authors
284
Institutions
Publications per year
2017–2026
111
Variants
Snm
Parents
373
1–5 of 373
1.5K
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284

National Yang Ming Chiao Tung University
Hsinchu, Taiwan
15 h-index
78 publications
2.8K citations
IBM (United States)
Armonk, United States
14 h-index
241 publications
8.3K citations
Purdue University West Lafayette
West Lafayette, United States
12 h-index
33 publications
1.8K citations
IMEC
Leuven, Belgium
9 h-index
75 publications
3.7K citations
University of Virginia
Charlottesville, United States
9 h-index
20 publications
936 citations
KU Leuven
Leuven, Belgium
9 h-index
21 publications
1.9K citations
Taiwan Semiconductor Manufacturing Company (Taiwan)
Hsinchu, Taiwan
8 h-index
111 publications
2.5K citations
Indian Institute of Technology Indore
Indore, India
8 h-index
17 publications
705 citations
1–8 of 284
28 publications · 1.3K citations
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19 publications · 1.3K citations
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16 publications · 2.6K citations
13
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8 publications · 205 citations
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JCSC · 7 publications · 169 citations
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