Static Noise Margin

Static Noise Margin is a metric in standard cell design that quantifies the maximum tolerable static noise voltage a logic gate can withstand without erroneous switching, distinguishing it from dynamic or transient noise measures by evaluating steady-state circuit stability.

373

Publications

14.9K

Citations

1.5K

Authors

284

Institutions

Publications per year

2017–2026

111

Variants

Snm

Authors

1.5K

  1. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    12 publications · 768 citations

    12

    h-index

  2. BH
    Benton H. Calhoun

    University of Virginia, United States

    9 publications · 873 citations

    9

    h-index

  3. VP
    Vita Pi‐Ho Hu

    National Yang Ming Chiao Tung University, Taiwan

    8 publications · 260 citations

    9

    h-index

  4. SK
    Santosh Kumar Vishvakarma

    Indian Institute of Technology Indore, India

    8 publications · 322 citations

    8

    h-index

  5. PS
    Pin Su

    National Yang Ming Chiao Tung University, Taiwan

    8 publications · 257 citations

    8

    h-index

1–5 of 1.5K

Venues

  1. IEEE Transactions on Electron Devices

    28 publications · 1.3K citations

    23

    h-index

  2. 16

    h-index

  3. IEEE Journal of Solid-State Circuits

    16 publications · 2.6K citations

    13

    h-index

  4. Microelectronics Journal

    8 publications · 205 citations

    8

    h-index

  5. Journal of Circuits Systems and Computers

    JCSC · 7 publications · 169 citations

    8

    h-index

1–5